1. Field of the Invention
The present invention relates to a compound semiconductor device such as an integrated circuit including a field effect transistor (FET), and more specifically, to a compound semiconductor device having improved resistance to a backgate effect from the surface of a substrate.
2. Description of the Related Art
A compound semiconductor typified by GaAs features higher electron mobility than that of Si and the development of compound semiconductor devices such as analog signal amplifier circuits having ultra-high-frequency elements such as an MES type field effect transistor, Schottky barrier diode or the like integrated thereon, logic gates, memories and the like is actively underway. However, for the implementation of these compound semiconductor devices, there are big problems to be solved such as a sidegate effect in which a potential difference between an element such as an FET on the front surface of a substrate and another element formed on the front surface of a substrate modulates the channel layer of that FET through the substrate and affects the element characteristics of the FET, for example, drain current. Another of such problems is a backgate effect which is caused by the potential difference between an element on the front surface of a substrate and an electrically grounded electrode on the back surface of the substrate.
FIG. 4 shows a differential amplifier circuit called xe2x80x9csource coupled FET logic (SCFL)xe2x80x9d which is often used in the digital or analog circuit of a compound semiconductor. This type of circuit is introduced on page 435 of xe2x80x9cGaAs DEVICES AND CIRCUITSxe2x80x9d, Plenum Press (Michael Shur, New York and London), for example. In FIG. 4, reference numeral 51 denotes a MESFET; 52, a resistor; 53, a diode; 54, a positive power source terminal; 55, a negative power source terminal; 56, an input terminal; and 57, an output terminal. This type of circuit employing a Si bipolar transistor in place of the FET is called xe2x80x9cemitter coupled logic (ECL)xe2x80x9d. Since both circuits operate at almost the same voltage and speed, they can be replaced with each other and selected according to the purpose of use and considering characteristics such as the steepness of the waveform of the circuit and power consumption, costs and the like.
To replace a Si bipolar device by a compound semiconductor device, it is necessary to match the shape of a circuit chip and the position of a bonding pad in order to use the same package. Generally speaking, since an ECL is grounded to a positive power source, a compound semiconductor device may be designed to be grounded not only to a negative power source but also to a positive power source in order to replace an Si bipolar device. That is, as shown in FIG. 2, the rear surface of an ordinary chip is bonded to a metal carrier 14 of a package which serves both for heat radiation and electrical grounding using a solder material 13 having a low melting point. It is possible that the carrier 14 is connected to either the positive power terminal 54 or the negative power terminal 55 of the SCFL shown in FIG. 4. In either one of the grounding systems, the source of the MESFET 51 on the input side of the SCFL is at an intermediate potential and a sidegate effect or a backgate effect caused by the operation of the circuit becomes a problem to be solved.
In IEEE Electron Device Letters, Vol. EDL-4, No.4, pp. 102-103, xe2x80x9cSelf-Aligned Sub-micron Gate GaAs Integrated Circuitsxe2x80x9d, an attempt to improve such a sidegate effect in a compound semiconductor device by implanting ions such as protons H+, boron ions B+ or oxygen ions O+ to form a defective region between FET elements formed on a semi-insulating GaAs substrate is proposed . The principle that the sidegate effect is improved by this method is described in the Technical Report of IEICE (the Institute of Electronics Information and Communication Engineers), Vol.91, No.321, ED 91-119, pp.19-24, xe2x80x9cGaAs Element Separation Mechanism by Defects Formed by Implantation of B+ Ionsxe2x80x9d.
However, since a defective region is formed only on the front surface of the substrate in this FET structure, it has no effect when the potential of the rear surface of the substrate varies. Further, when the total area of adjacent electrodes on the front surface of the substrate, for causing a sidegate effect, is much larger than that of the FET concerned, the effect of the defect region is weakened, whereby the amount of a field generated through a deep portion of the substrate increases and a backgate effect appears, thereby causing fluctuations in the characteristics of the FET.
Several proposals for forming a layer having a deep level under an FET channel layer have been made to improve backgate voltage resistance of the substrate side.
FIG. 5 is a sectional view of a semiconductor device (to be referred to as xe2x80x9cfirst conventional examplexe2x80x9d hereinafter) proposed in IEEE, Transactions on Electron Devices, Vol.37, No.1, 1990, pp.46-50, xe2x80x9cAnomalies in MODFET""s with a Low-Temperature Bufferxe2x80x9d. In this conventional example, a low-temperature growth i-type GaAs layer 62, a normal-temperature growth i-type GaAs layer 63 and an n-type GaAs layer 64 are grown on a semi-insulating GaAs substrate 61 sequentially and a source electrode 66, a gate electrode 67, a drain electrode 68 and a sidegate 69 are formed on the n-type GaAs layer 64 to separate these elements by an ion implanted defect layer 65. The term xe2x80x9csidegatexe2x80x9d as used herein defines an electrode adjacent to an affected FET (FET shown at the center of the figure) and having a sidegate effect on the FET and generally refers to the conductive region or electrode of an FET or diode.
The MBE growth of GaAs is generally carried out at around a temperature of 600xc2x0 C. However, in this conventional example, part of a buffer layer (62) is formed at a growth temperature of 200 to 300xc2x0 C. to generate defects (deep levels) in this layer with an excessive amount of arsenic (As).
As a second conventional example, as shown in FIG. 6, formation of a layer doped with deep level generating impurities by continuous epitaxial growth is proposed in Laid-open Japanese Patent Application (KOKAI) No. Hei 3-3336. In this conventional example, an i-type GaAs buffer layer 72, a 400-nm-thick Cr doped GaAs layer 73 having a Cr concentration of about 5xc3x971016 cmxe2x88x923 as an impurity for generating a deep level, a p-type GaAs layer 74 and an n-type GaAs layer 75 are epitaxially grown sequentially on a semi-insulating GaAs substrate 71, and a source electrode 76, a gate electrode 77 and a drain electrode 78 are formed on the n-type GaAs layer 75. Fe (iron), Ni (nickel) or oxygen may be used in place of Cr. An embodiment in which the Cr doped GaAs layer 73 is inserted between the semi-insulating GaAs substrate 71 and the i-type GaAs buffer layer 72 is shown in the document as well.
As a third conventional example, as shown in FIG. 7, the formation of an ion implanted defect layer 82 at a position deeper than an active layer in a semi-insulating GaAs substrate 81 is proposed in Laid-open Japanese Patent Application (KOKAI) No. Hei 4-49627. In this conventional example, after the ion implanted defect layer 82 is formed, silicon is selectively implanted to form an n-type GaAs layer 83 and a source electrode 84, a gate electrode 85 and a drain electrode 86 are formed on the n-type GaAs layer 83. Boron is selected as an impurity for forming the ion implanted defective layer 82 and implanted at 150 keV in an amount of 1xc3x971015 cmxe2x88x922 ions. Protons or oxygen ions may be implanted in place of boron ions.
As a fourth conventional example different from the above two, as shown in FIG, 8, the formation of an insulating film 92 between a semi-insulating GaAs substrate 91 and a rear-surface electrode 93 is proposed in Laid-open Japanese Patent Application (KOKAI) No. Sho 63-48869. An n-type GaAs layer 96 is formed on the front surface of the semi-insulating GaAs substrate 91 by ion implantation, and a source electrode 97, a gate electrode 98 and a drain electrode 99 are formed on the n-type GaAs layer 96. A rear-surface electrode 93 is soldered to a carrier 95 by a solder material 94. The purpose of forming the insulating film 92 is to improve withstand voltage and gain by suppressing a leak current into the substrate. As a material for the insulating film, SiN, SiO, SiON or the like may be employed.
In the first conventional example described above, since a low crystalline quality layer must be formed by low-temperature epitaxial growth, defects easily spread into the top layer, the electron mobility of the channel layer is reduced, and the characteristics of the FET deteriorate. In this conventional example, in order to obtain sufficient backgate resistance, it is necessary to reduce the epitaxial growth temperature and increase the thickness of a low-temperature epitaxial layer. Therefore, it is difficult to obtain an active layer having high carrier mobility and excellent crystallinity so that the characteristics of an FET such as gm and uniformity are unsatisfactory.
In the second conventional example, the carrier is excellent in mean free path (Debye length) and the effect of suppressing a backgate effect is small with a Cr concentration (5xc3x971016 cmxe2x88x923) and a film thickness of 400 nm described as the embodiment. When the concentration of Cr is increased to improve the backgate effect resistance, the crystallinity deteriorates with the result that the same problem as in the first embodiment occurs and at the same time, a shallow level as well as defects are produced, thereby reducing resistivity disadvantageously. Also, when the thickness of the layer is increased, the growth time is prolonged, thereby reducing manufacturing productivity.
Further, in the third conventional example, since the acceleration energy of an ion implanter which is commonly used is about 200 keV, even boron ions that are light-weighted can be implanted to only a depth of 1 xcexcm. Since the crystallinity of the substrate and the Debye length are recovered by a heat treatment for activating the channel layer, there is no effect of suppressing a backgate effect as in the second conventional example. If the temperature of such heat treatment is lowered, the activation of the channel layer is incomplete and the characteristics of an FET deteriorates. Although it is conceivable that boron ions may be implanted after the activation of the channel layer, a large number of defects are disadvantageously introduced into the active layer by this ion implantation as described in the document.
Finally, in the fourth conventional example, it is necessary to reduce the thickness of the inserted insulation film because of poor heat conductivity. However, when the thickness is reduced, the capacitance increases. A laminated structure of an insulating film and a semi-insulating substrate constitutes a serial body of a capacitor and a resistor. Because the capacitance of the insulating film is large, when the source potential of an FET which is at an intermediate level in the SCFL of FIG. 4 instantaneously makes a big shift to a positive value due to the operation of the circuit, a backgate effect is produced for an instance to decrease a channel current (drain current), thereby delaying the change of a source potential, as a change in the potential of the interface between the channel and the substance right under the gate is delayed by the capacitance of the insulating film. Therefore, the insertion of a dielectric film having high resistance under the surface of a substrate has no effect of improving backgate resistance.
It is therefore an object of the present invention to suppress a backgate effect without affecting an FET channel layer and reducing productivity.
The above object can be attained by forming a defect-rich defective layer (hereinafter called the xe2x80x9cdefect layerxe2x80x9d) on the rear surface of a semi-insulating substrate by ion implantation. The ion implantation induces crystalline defects capable of acting as carrier recombination centers in these defect layers.
A compound semiconductor device according to the present invention is characterized by comprising a field effect transistor element formed on the front surface of a semi-insulating semiconductor substrate and a defective layer formed on the rear surface of the semi-insulating semiconductor substrate by ion implantation.
Ions to be implanted to form the above defective layer are of B (boron), N (nitrogen), O (oxygen) or F (fluorine) ions.
The ability of the 1 xcexcm thick defective layer formed by ion implantation as a recombination center is much higher than those of impurities contained in the crystals such as Cr, Fe, Ni and O which are present in the conventional examples. Therefore, holes injected into the semi-insulating substrate from a front-surface electrode which changes by the operation of the circuit can be eliminated at a high speed. When this defective layer is formed on the rear surface of the substrate, even if the source potential is changed, the potential of the interface between the channel and the substrate right under the gate is not pulled by the potential of the rear surface of the substrate, thereby suppressing a backgate effect. Further, since the holes accumulated in the substrate are eliminated at a high speed, pulse response is improved as well.
In the compound semiconductor device according to the present invention, ions are implanted into the entire rear surface of the substrate after an FET element is formed on the front surface of the substrate. Therefore, the number of additional steps is only one.
Further, when a deep level layer is formed under the channel layer of an FET as in the first to third conventional examples, the channel layer is affected by the deep level layer and the characteristics of the FET deteriorate. On the other hand, since ions are implanted onto the rear surface of the substrate in the present invention, they do not affect the characteristics of an FET on the front surface of the substrate.
It is further noted that the thickness of the substrate is generally reduced by polishing the rear surface thereof before a chip is obtained therefrom. Since the depth of damage caused by such mechanical polishing is much smaller than that of damage caused by charged particles of implanted ions because energy is much smaller and there is almost no ability as a recombination center.